| TYPE | DESCRIPTION |
| Part Status | Active |
| Pin Count | 133 |
| Program Memory Type | ROMLess |
| Speed Grade | 50 |
| Number of Macro Cells | 192 |
| Automotive | No |
| Data Gate | No |
| Device System Gates | 8000 |
| ECCN (US) | 3A001.a.2.c |
| EU RoHS | Supplier Unconfirmed |
| Family Name | ispLSI? 1000 |
| HTS | 8542.39.00.01 |
| Individual Output Enable Control | Yes |
| In-System Programmability | Yes |
| Maximum Clock to Output Delay (ns) | 16 |
| Maximum Internal Frequency (MHz) | 58.8 |
| Maximum Number of User I/Os | 96 |
| Maximum Operating Current (mA) | 260 |
| Maximum Operating Supply Voltage (V) | 5.5 |
| Maximum Operating Temperature (°C) | 125 |
| Maximum Propagation Delay Time (ns) | 26 |
| Minimum Operating Supply Voltage (V) | 4.5 |
| Minimum Operating Temperature (°C) | -55 |
| Mounting | Through Hole |
| Number of Flip Flops | 288 |
| Number of Global Clocks | 4 |
| Number of Logic Blocks/Elements | 48 |
| PCB changed | 133 |
| PPAP | No |
| Programmability | Yes |
| Reprogrammability Support | Yes |
| Standard Package Name | PGA |
| Supplier Package | CPGA |
| Supplier Temperature Grade | Military |
| Tradename | ispLSI |
| Typical Operating Supply Voltage (V) | 5 |
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